Electronic designs may be large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing electronic designs on a target device, synthesis, placement, and routing utilizing available resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of electronic design automation (EDA) tools to manage and optimize designs. EDA tools perform the time-consuming tasks of synthesis, placement, and routing on a target device.
Some EDA tools also performing timing analysis on a design. The timing analysis may be performed after synthesis, placement, and/or routing in order to confirm that the design for the system meets timing requirements. Timing analysis may also be performed after synthesis, placement, and/or routing in order to evaluate solutions generated by one or more of the procedures. The results from timing analysis may be used to re-run one or more of the procedures in efforts to improve a solution. The main task of timing analysis is the computation of slack values. Slack may be defined as the difference between a data arrival time and a data required time.
The procedures used for computing slack values for a design may require a significant amount of processor execution time. When timing analysis is used to compute slack for a plurality of stages in the design flow, significant delays may be incurred in the design process.
Thus, what is needed is an EDA tool that is able to perform parallel slack computation.